Pursuant to 35 U.S.C. 119(a)-(d), this application claims priority from Taiwanese application no. 090120068, filed with the Taiwanese Patent Office, Taiwan, on Aug. 16, 2001.
1. Field of the Invention
The present invention relates in general to an electrostatic discharge (ESD) protection circuit utilizing a semiconductor-controlled rectifier (SCR). In particular, the present invention relates to an ESD protection circuit having a high triggering threshold.
2. Description of the Related Art
ESD protection is an important issue for semiconductor products, and is especially crucial during manufacture of minimized complementary metal oxide semiconductors (CMOSs). Breakdown voltages of gate oxide layers in MOS transistors have decreased as the manufacturing process has improved. In order to protect the gate oxide layer from ESD stress, an ESD protection circuit is formed at each input/output (I/O) port as a general security measure.
A semiconductor-controlled rectifier (SCR) is often used as an ESD protection component for its low holding voltage. FIG. 1 shows a cross section of a conventional lateral SCR. As shown in FIG. 1, a PNPN structure is formed by a P+ doped region 14, an N-well 12, a P-substrate 10 and an N+ doped region 18. The N-well 12 is coupled to the P+ doped region 14 through an N+ doped region 16 to become an anode of the SCR. The P-substrate 10 is coupled to the N+ doped region 18 through a P+ doped region
to become a cathode of the SCR. FIG. 2 is a voltage-current diagram of the conventional SCR in FIG. 1. The triggering voltage is approximately equal to the junction-breakdown voltage between the N-well 12 and the P-substrate 10 (approximately larger than 10V). The holding voltage Vhold is about 1V. The thermal energy generated by an ESD protection component during an ESD event is approximately equal to IESDxc3x97VESD. The voltage VESD generated by a conventional SCR during an ESD event is relatively low, approximately equal to the holding voltage Vhold. Therefore, a conventional SCR conducts large current without becoming overheated and thus is suitable for ESD protection.
It is noted that the triggering current Itrig of a conventional SCR is rather small as shown in FIG. 2. When used as an ESD protection component at a pad, the conventional SCR is easily triggered and latched up by noise during normal power operations. The pad is clamped to a low voltage (xcx9cVhold) and signal transmissions at the pad are interrupted.
The ESD protection circuit of the present invention has a high triggering threshold to overcome the problems caused by latch-up.
An ESD protection circuit of the present invention having a high triggering threshold comprises a semiconductor-controlled rectifier (SCR) and a bipolar-junction transistor (BJT). The SCR comprises an anode, an anode gate, a cathode gate and a cathode. The anode is coupled to a first pad. The cathode gate and the cathode are coupled to a second pad. The BJT is parasitic under a metal-on-semiconductor (MOS) transistor and has a collector and an emitter. Either the collector or the emitter is coupled to the anode gate, and the other is coupled only to the second pad.
Another ESD protection circuit of the present invention comprises a gate-grounded NMOS transistor and a lateral SCR. The lateral SCR comprises a substrate having a first conductivity type, a well region having a second conductivity type, a first doped region having the first conductivity type, and a second doped region having the second conductivity type. The gate-grounded NMOS transistor comprises a drain coupled only to the well region, and a gate and a source coupled together. The first doped region is coupled to a first pad. The second doped region, the source and the gate of the gate-grounded NMOS transistor are coupled to a second pad.
The ESD protection circuit of the present invention provides good ESD protection and prevents latch-up caused by accidental noise during normal power operations.